To ensure a high fault coverage, integrated circuits (ICs) are often tested at the speed such circuits will be used by customers (i.e., at-speed testing). Current memory interfaces, such as the DDR2 memory interface, presently run at 800 mbps. Using conventional Automated Test Equipment (ATE) approaches at such speeds would be prohibitively expensive.
One way of implementing at-speed testing is with an internal loopback. Such a system would send signals through multiplexers allowing such signals to be read back into a built-in self test (BIST) logic. Some conventional systems use an internal loopback for testing a DDR interface. Such a system also uses a multiplexer. Such a system has the disadvantage of not testing the I/O buffer at high speeds.
Current solutions implement the impedance of the transmission path by terminating the ATE pin electronics (PE) close to 50 ohms. Such termination helps with loopback testing, but does not allow for DC testing. Also, the transmission path must be properly terminated. The simplest termination is a 50-ohm resistor to ground. However, the signal has to be connected from the device under test (DUT) to the ATE PE card. In such a system two DUT boards need to be made, one with the 50-ohm termination and the other with the connection from DUT to PE card. Such a solution has the disadvantage that in a two-board system, two-pass testing must be done, approximately doubling the cost and duration of testing.
It would be desirable to implement a system that terminates I/Os by implementing a test termination card that allows both DC testing and external loopback BIST testing.